The following example demonstrates an audio filtering model that applies the same filter on the left and right channels. Various optimizations can require clock rates faster than indicated in the original model. Multiple synchronous clocks can be useful even for a design with only a single Simulink rate. Multiclock Mode and HDL Coder Optimizations As with single clock mode, this information is presented both in the HDL DUT file comment block and the HTML report. It describes the relative clock ratio between each clock and the fastest clock in the model. This table has one entry for each primary DUT clock. The contents of the Clock Summary are different in multiple clock mode. # HDL check for 'hdlcoder_clockdemo' complete with 0 errors, 1 warnings, and 1 messages.Ĭlock Summary Information in Multiclock Mode
Best hardware multiclock code#
Either change the ClockInputs property at the command line using makehdl or change the Clock inputs setting to Multiple on the HDL Code Generation > Global Settings tab of the Configuration Parameters dialog box. To generate multiple synchronous clocks for this design, the ClockInputs property must be set to multiple. Generating Synchronous Multiclock HDL Code Any time a HTML report is generated, the Clock Summary Report is also generated. The report also contains a table listing each user output signal and its associated clock enable output signal. In single clock mode, this report contains a table detailing the sample rates for each clock enable output signal. The file comment block in the HDL DUT code contains Clock Summary information. # HDL check for 'hdlcoder_clockdemo' complete with 0 errors, 0 warnings, and 1 messages.Ĭlock Summary Reporting in Single Clock Mode
# Generating HTML files for code generation report at hdlcoder_clockdemo_codegen_rpt.html # Code Generation for 'hdlcoder_clockdemo' completed. # Generating package file hdlsrc/hdlcoder_clockdemo/DUT_pkg.vhd. # Working on hdlcoder_clockdemo/DUT as hdlsrc/hdlcoder_clockdemo/DUT.vhd.
# Code Generation for 'DUT_tc' completed. # Working on DUT_tc as hdlsrc/hdlcoder_clockdemo/DUT_tc.vhd. # Begin VHDL Code Generation for 'DUT_tc'. # Begin VHDL Code Generation for 'hdlcoder_clockdemo'. # Begin model generation 'gm_hdlcoder_clockdemo'. # Working on the model 'hdlcoder_clockdemo'. # Begin compilation of the model 'hdlcoder_clockdemo'. # Running HDL checks on the model 'hdlcoder_clockdemo'. # Using the config set for model hdlcoder_clockdemo for HDL code generation parameters. # Generating HDL for 'hdlcoder_clockdemo/DUT'. The filter's input is also presented as an output for this example to present a model with output signals running at different rates. The first example uses a multirate CIC Interpolation filter in single clock mode. For example, in a multirate model consisting of Downsample block, add a unit delay block after the Downsample block to generate the clock port of that downsampling rate. If the sequential logic is not present at a particular Simulink rate, HDL Coder does not generate separate clock port for that rate. When using multiple clocks for multirate model, it is recommended to add sequential logic such as delay block at each Simulink rate. A multiple clock model may require multiple timing controllers. These out of phase signals are generated with a timing controller. Transitions between rates require clock enables at a given rate that are out of phase with that rate's clock. Each clock port corresponds to a separate rate in the model. In synchronous multiple clock mode, the generated code has a set of clock ports as primary inputs to the DUT. Each output signal rate is associated with a clock enable output signal that indicates the correct timing to sample the output data. Each generated clock enable is an integer multiple slower than the primary clock rate. The timing controller generates a set of clock enables with the necessary rate and phase information to control the clocking for the design. In single clock mode, if multiple rates exist in the Simulink model, a timing controller is created to control the clocking to the portions of the model that run at a slower rate. By default, HDL Coder creates an HDL design that uses a single clock port for the DUT. The other mode generates a synchronous primary clock input for each Simulink® rate in the DUT. One mode generates a single clock input to the Device Under Test (DUT).
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